1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having an internal voltage down converter, which is adaptable to external power supplies of different voltage levels.
2. Description of the Background Art
Semiconductor memory devices come to have ever higher density and ever higher degree of integration as elements constituting the devices have been reduced in size. For example, under 0.4 micron design rule, thickness of a gate oxide film in an insulated gate type field effect transistor (hereinafter referred to as an MOS transistor) which is one of the elements constituting the device is about 100 .ANG., which is extremely thin as compared with the conventional ones.
As it is miniaturized, withstanding capability of the gate oxide film in the MOS transistor has been degraded. It does not present any problem when an external power supply of 3.3V, which is now dominant, is used. However, when an external power supply of 5V, which has been used conventionally, is applied, the withstanding capability is exceeded, and therefore reliability can not be ensured.
Therefore, it is a general practice to lower the external power supply voltage internally and to use the internal power supply voltage to ensure reliability of the elements, when an external power supply of 5V is used.
FIG. 6 is a schematic block diagram showing an overall structure of a semiconductor memory device using a conventional external power supply of 5V. A semiconductor memory device 200 includes an external power supply pad P4, an internal voltage down converter 50 (hereinafter referred to as VDC 50), an internal circuitry 52, and an external power supply using circuit 53.
External power supply pad P4 is connected to the external power supply and receives external power supply voltage ExtVcc from the external power supply. VDC 50 is connected to external power supply pad P4 and a ground node Vss, down converts the external power supply voltage ExtVcc applied to external power supply pad P4 and generates an internal power supply voltage intV.
Internal circuitry 52 is connected to VDC 50. An example of the internal circuitry 52 is a memory cell array including a plurality of memory cells. Therefore, an MOS transistor which is an element of the memory cell array operates using the internal power supply voltage intV provided by down converting external power supply voltage ExtVcc as its operational power supply.
External power supply using circuit 53 operates receiving external power supply voltage ExtVcc. One example is a circuit for processing related to data input/output.
When the external power supply is 3.3V, internal circuitry 52 is directly connected to external power supply pad P4. Conventionally, a current mirror type internal voltage down converter has been known as such VDC 50.
FIG. 7 is a schematic block diagram showing an overall structure of the conventional current mirror type internal voltage down converter. VDC 50 includes a P channel MOS transistor (hereinafter referred to as PMOS) MP6, and a current mirror type differential amplifier 51 for switching PMOS MP6.
Differential amplifier 51 receives at its negative input a reference voltage VREF supplied from a reference voltage generating circuit, not shown. Its positive input is connected to one conduction terminal of PMOS MP6 through a node E, and receives internal power supply voltage intV generated on node E.
Differential amplifier 51 compares internal power supply voltage intV on node E and reference voltage VREF, amplifies and outputs a control voltage VOUT.
PMOS MP6 has the other conduction terminal connected to external power supply pad P4 and receives external power supply voltage ExtVcc from the external power supply. The one conduction terminal is connected to differential amplifier 51 through node E, as described above. Its gate receives control voltage VOUT which is an output from differential amplifier 51.
Based on control voltage VOUT, PMOS MP6 adjusts current supply from external power supply voltage ExtVcc to node E. As a result, voltage level of internal power supply voltage intV on node E is kept constant.
However, the conventional semiconductor memory device 200 shown in FIG. 6 having the above described structure is adaptable to only one external power supply.
Meanwhile, though external power supply voltage of 3.3V has come to be dominant instead of 5V for a semiconductor memory devices, the power supply of 5V is still required for some uses.
Therefore, in order to be compatible for different external power supplies, it is necessary in the step of manufacturing the semiconductor memory device to produce mask patterns in accordance with voltage levels of the external power supplies (more specifically, two different mask patterns for the external power supply of 3.3V and the external power supply of 5V).
Further, the conventional VDC 50 used for the external power supply of 5V has the following problem.
More specifically, VDC 50 is adapted to adjust voltage level of internal power supply voltage intV based on feedback control. Therefore, there is a time lag from the feedback of internal power supply voltage intV to the differential amplifier 51 until the voltage level of the internal power supply voltage intV actually changes.
When the time lag is large, current supply from external power supply voltage ExtVcc to node E shown in FIG. 7 cannot follow, resulting in temporary voltage drop, and hence the speed of operation cannot be ensured. The same phenomenon is observed when the external power supply voltage ExtVcc lowers by some cause.
Further, since VDC 50 is formed of a feedback loop, when the feedback cannot follow the change in the internal power supply voltage intV, internal power supply voltage intV would start oscillation.
Further, for the VDC 50, it is necessary to adjust reference voltage VREF in advance, and therefore the step of laser trimming cannot be reduced.
Further, current consumption of the VDC is rather high, and therefore current consumption cannot be reduced at the standby state.
Further, in order to realize stable operation of VDC 50, a relatively high capacitance is necessary, and therefore the chip size cannot be made smaller.
These problems are common in all semiconductor memory devices including VDC 50. However, the influence is especially serious for a high speed static random access memory (hereinafter referred to as high speed SRAM) when operation specification thereof is to be satisfied.